Wiring Edge-Disjoint Layouts

We consider the wiring or layer assignment problem for edge-disjoint layouts. The wiring problem is well understood for the case that the underlying layout graph is a square grid (see 7]). In this paper, we introduce a more general approach to this problem. For an edge-disjoint layout in the plane resp. in an arbitrary planar layout graph, we give equivalent conditions for the k-layer wirability. Based on these conditions, we obtain linear-time algorithms to wire every layout in a tri-hexagonal grid, respectively every layout in a tri-square-hexagonal grid using at most ve layers. The wiring problem consists in converting a two-dimensional edge-disjoint layout into a three-dimensional vertex-disjoint layout. Wiring edge-disjoint layouts is a fundamental and classical problem in VLSI-design. Typically, the general layout problem in VLSI-design consists of two phases, the placement and the routing. Often, the routing phase is again divided into two steps. First, a two-dimensional layout is constructed satisfying certain conditions induced by the underlying layout model. This layout describes the course of the wires connecting the corresponding terminals. In the second step, the wiring step or layer assignment step, the edges of the wires are assigned to diierent layers to avoid physical contacts between diierent wires. The layout can be viewed as a projection in the plane of this nal three-dimensional wiring. In connection with graph drawing, the wiring problem is of interest as well. There, an edge-disjoint embedding of a graph is given. The problem consists in a visualization of the graph by a three-dimensional vertex-disjoint embedding whose projection in the plane is again the edge-disjoint embedding of the graph. Consider an edge-disjoint layout in the plane resp. in a planar graph. Such a layout may be an edge-disjoint realization of nets or an edge-disjoint embedding of a graph. The construction of edge-disjoint layouts is a fundamental problem. For an overview we refer to 8]. Then the wiring problem can be described as follows. There is a number of graphs isomorphic to the layout, called layers. Each path, called wire, of the layout is realized by a sequence of subpaths in diierent layers such that two diierent wires are vertex-disjoint. A vertical connection between layers, a via, is used at each layer change. The main optimization goal is to minimize the number of layers. Several results have been obtained for the wiring problem for edge-disjoint layouts in regular Most of these results are based on …